TSMC by the Numbers: 70% Foundry Share, 58% of Revenue from AI Servers — a Deep Dive into the Business Behind the Chip Monopoly

This article analyzes TSMC as a business — where it earns, why it holds over 70% of the global foundry market, and where its risks lie — using the company's investor-relations disclosures and research-firm data. If you first want the big picture of why TSMC is indispensable to the world, start with Why TSMC matters: the one company the world's phones and AI cannot exist without. This is an analysis of technology and industry, not investment advice.

What is TSMC, and where did it come from?

TSMC is the world's largest foundry — a company that takes on only the manufacturing of semiconductors. In 1987, Morris Chang founded it on a business model that was heretical at the time: own no products, and commit entirely to manufacturing. This was the world's first pure-play foundry, and it is the origin of the division of labor that defines the semiconductor industry today.

Until then, chipmakers were by default IDMs (integrated device manufacturers — companies that handle everything from design through manufacturing in-house). By creating a company that would take on manufacturing alone, TSMC made it possible for fabless companies — design specialists with no factories — to exist at all. Put simply: without TSMC, Apple and NVIDIA would each have needed to build their own fabs. This design-manufacturing split is covered in detail in how the industry divided into companies that design and companies that build (in Japanese).

Where does TSMC earn its money? (revenue mix)

TSMC's biggest earner is no longer smartphones — it is HPC (high-performance computing, meaning AI and server chips). For full-year 2025, revenue by platform broke down as follows.

(Source: TSMC)

Only a few years ago, smartphones were the largest pillar; by 2025, HPC had overtaken them to reach roughly 60% of revenue. The explosive growth of AI chips is rewriting the earnings structure of the manufacturer itself. For what counts as an AI chip, see what is an AI semiconductor (in Japanese).

By process node (degree of miniaturization), the earnings center of gravity sits firmly at the leading edge.

(Source: TSMC)

Advanced nodes (7nm and below) accounted for 74% of wafer revenue, up from 69% in 2024. The finer the chip, the higher the price per wafer and the fewer the companies able to make it — which is what lifts TSMC's margins. Indeed, the full-year 2025 gross margin reached 59.9% and the net margin 45.1% (TSMC).

Why is TSMC technologically dominant?

TSMC's technical strength lies in bringing each leading-edge node into volume production earlier than anyone else, at higher yield (the share of good chips per wafer). The higher the yield, the more good chips come off each wafer, and the lower the unit cost. Because contract work from around the world concentrates enormous volume in its fabs, experience accumulates, yield climbs, and better yield attracts still more orders — a self-reinforcing cycle.

The second pillar is fine patterning with EUV (extreme ultraviolet lithography). EUV draws circuits with light at a 13.5nm wavelength — the most advanced lithography technology in existence — and by deploying it at scale to put next-generation nodes into production first, TSMC has widened its lead over Samsung and Intel.

The third pillar is advanced packaging. An AI chip is not one giant die; it is built by placing multiple chiplets (small dies split up by function) and HBM (stacked high-bandwidth memory) side by side on a single substrate.

The flagship technology for arranging and bonding these parts is TSMC's CoWoS, which is indispensable to NVIDIA's AI accelerators. Controlling not just the front end (chip fabrication) but the leading edge of the back end (assembly and packaging) as well is a major point of separation from competitors.

Whom does TSMC depend on in the supply chain?

TSMC stands at the industry's central junction in both directions — whom it builds for, and whom it depends on. Its customers (buyers) are the world's major design houses: Apple, NVIDIA, AMD, Qualcomm. TSMC manufactures their designs and delivers the chips.

At the same time, TSMC itself depends heavily on equipment and materials suppliers (sellers). Leading-edge EUV lithography machines are supplied by exactly one company in the world: ASML of the Netherlands. However much TSMC wants to push the leading edge, it cannot move unless ASML ships machines. Wafer substrates, photoresists (light-sensitive materials) and specialty gases are likewise concentrated in a handful of suppliers — many of them Japanese. TSMC occupies the manufacturing position in the value chain while resting on this upstream base of equipment and materials. For the industry-wide flow, see how the semiconductor industry works (in Japanese); for who those upstream Japanese suppliers are, see Japan's semiconductor equipment makers, mapped.

Where does TSMC stand in the market, and what does competition look like?

TSMC's position in the foundry market is overwhelming. According to TrendForce, TSMC held 70.2% of global foundry revenue in the second quarter of 2025 — number one in the world, with second-place Samsung at 7.3%. Restricted to advanced nodes, its share is higher still (TrendForce).

Here's the competitive structure in foundry markets.

For how the foundries fit into the broader company landscape, see the six roles that make the chip industry click (in Japanese). TSMC's advantage arises from an asymmetric structure: it is hard to enter against, hard to substitute for — yet dependent on its upstream equipment and materials suppliers.

Where are TSMC's weaknesses and risks?

The biggest risk is the concentration of production in Taiwan. Because leading-edge manufacturing is packed into a small number of Taiwanese fabs, an earthquake or a conflict over Taiwan could halt the global supply of smartphones, AI hardware and cars all at once. This single-point concentration is the source of the geopolitical tension driving countries to compete for TSMC fabs.

The second risk is the ballooning scale of capital expenditure. A leading-edge fab now costs tens of billions of dollars per site, and TSMC's capex budget for 2026 is expected to reach 52 to 56 billion U.S. dollars (TSMC). Whether that investment pays off depends on AI demand continuing to grow as projected. HPC at 58% of revenue is a strength — and, flipped around, a heavy dependence on the AI cycle.

What has TSMC been doing lately?

TSMC is now pursuing two things at once: diversifying its Taiwan concentration risk and advancing the leading edge. Overseas, it announced an expansion of its Arizona investment to a total of 165 billion U.S. dollars and has begun volume production there. In Japan, the first Kumamoto fab is in operation — the story behind that site is told in why TSMC built a fab in rural Kumamoto — and in Dresden, Germany, it is building its first European fab, Fab 24 (TSMC). Some overseas plans, however, are being re-timed in response to demand.

On the technology front, N2 (the 2nm-class node), the next leading-edge generation, entered volume production within 2025. N2 is TSMC's first node to adopt the GAA (gate-all-around) transistor architecture, a complete redesign of the transistor structure. The enhanced N2P and A16 (a 1.6nm-class node featuring backside power delivery, which feeds power from the back of the chip) are scheduled for volume production in the second half of 2026 (TrendForce). At the frontier of miniaturization, TSMC still leads the field.

Summary

• TSMC, founded in 1987, is the world's first and largest pure-play foundry. It owns no products of its own and dedicates itself to manufacturing chips for design companies such as Apple and NVIDIA. Full-year 2025 revenue was $122.4 billion, up 35.9% year on year.
• Its biggest earner is HPC (AI and server chips), at 58% of full-year 2025 revenue. Advanced nodes (7nm and below) accounted for 74% of wafer revenue.
• Its foundry market share was a dominant 70.2% in Q2 2025 (TrendForce). Yield at EUV-based advanced nodes and advanced packaging such as CoWoS form the moat.
• The biggest risks are the concentration of production in Taiwan (geopolitics) and capital spending swelling past $50 billion a year. Production is being diversified to Arizona, Kumamoto in Japan, and Dresden in Germany — at higher cost.
• At the technology frontier, N2 (2nm-class) entered volume production in 2025 and A16 (1.6nm-class) is slated for the second half of 2026, keeping TSMC at the head of the miniaturization race.