The full picture of government funding and the production plan is covered in Japan Has Committed ¥2.35 Trillion to Rapidus. Here we focus on neither money nor technology, but on how to gather customers and an ecosystem.
Even if Rapidus owns a leading-edge 2nm fab, it means nothing unless companies design chips for it. Designing a semiconductor requires a toolkit called a PDK — the manual for how to draw blueprints for that specific fab. Rapidus has talked with more than 60 companies and moved to handing this PDK to about 10 of them. Gathering customers and designers is actually harder than building the fab.
Also see: The Structural View (Investor)
Rapidus has demonstrated 2nm prototypes and secured an additional 150 billion yen IPA investment (2026-06-05, cumulative 250 billion yen), but the key to the business is customers and ecosystem. It is in talks with 60-plus companies centered on HPC/AI/edge, with PDKs provided to about 10 (media-reported). Differentiation targets high-mix low-volume, short-TAT production rather than TSMC-style scale. The real evaluation point is the 2H fiscal 2027 volume ramp, when utilization, yield and customer count converge. Earning trust in the EDA/IP ecosystem is the largest non-capital barrier.
What is a PDK, and why does handing one over matter?
A foundry is a fab that manufactures semiconductors designed by other companies. What often gets overlooked: to design for a fab, a customer needs that fab's specific way of drawing blueprints. The package that captures it is the PDK (Process Design Kit).
A PDK contains transistor characteristics data, design rules such as wiring spacing, and component libraries for verification. Only with these can a designer draw circuits for that fab's manufacturing process. Put the other way around, handing over a PDK is the act of opening the door to a customer: design on our 2nm process. The fact that Rapidus has moved to providing PDKs to about 10 companies shows customer acquisition has advanced from talks to a phase where customers can actually try designing.
How far along is Rapidus in gathering customers?
According to Rapidus president Atsuyoshi Koike, the company is in talks with more than 60 prospective customers, mainly in HPC (high-performance computing), AI and edge, and provides PDKs to about 10. The meaning of these numbers needs precision: neither 60 nor 10 is a count of signed contracts. They are companies in discussion, or companies that have advanced to trial design.
The movement still matters, because a foundry business grows into volume orders only through the accumulation of exactly this kind of groundwork. The government is also backing front-end and back-end technology development toward 2nm volume production in the second half of fiscal 2027, which lets Rapidus bring technical and financial credibility to the negotiating table.
Why are customers harder than the fab?
A leading-edge-node fab costs trillions of yen just to build. But without customers designing and manufacturing there, utilization never rises and the enormous investment cannot be recouped. This is the structural difficulty facing any new foundry.
Chip design depends on an ecosystem: EDA (electronic design automation) tools for drawing circuits, and IP (design assets) — pre-built functional blocks that designers reuse. TSMC, the world's largest foundry, spent decades building this environment and locking in a vast base of customers and design assets. A new entrant like Rapidus must earn customer trust in its design environment from zero. A fab (hardware) can be built with money; a design ecosystem (software and trust) cannot be stacked up overnight. That is why customers are harder than fabs.
How is this different from TSMC? The high-mix, short-TAT bet
The Rapidus strategy differs from TSMC's model of driving unit prices down through mass production. What Rapidus champions is high-mix low-volume production with short TAT (Turn Around Time — the period from design to prototype). By drastically compressing design-to-prototype schedules and cycling many product types quickly in small lots, it aims to capture the diverse AI and edge demand that one-size-fits-all mass production struggles to serve.
| Dimension | TSMC model (mass production) | Rapidus aim |
|---|---|---|
| Lot size | Large lots, production efficiency first | High-mix, low-volume |
| Turnaround | Standard TAT | Short TAT (accelerated design-to-prototype) |
| Main target | Large committed demand | Diverse AI, edge and HPC demand |
| Source of competitiveness | Scale and price | Speed and flexibility |
Whether this bet reaches profitability will be tested from the second half of fiscal 2027 onward, when volume-production yield (the share of good chips) and customer count must both materialize. The 2nm GAA-transistor prototyping is progressing, but commercial viability will be decided over the next few years.
For the full picture of the company, see Rapidus Explained: Japan's Last Bet on a 2nm Foundry. What the label 2nm actually means as a node name is covered in 2nm no longer means a length of 2 nanometers (in Japanese), and the details of state funding and the production plan are in Japan Has Committed ¥2.35 Trillion to Rapidus.
Key takeaways
- What decides a foundry's fate is customers, not the fab. Rapidus is in talks with more than 60 companies and now provides PDKs to about 10 (media-reported).
- A PDK (process design kit) is the specification set needed to design on a fab's process — handing it over is the practical entry point of customer acquisition.
- Chip design needs an ecosystem of EDA (design tools) and IP (design assets), which TSMC spent decades building.
- Rapidus is betting on high-mix low-volume, short-TAT production rather than mass production, targeting diverse AI and edge demand.
- Whether the strategy pays off will be tested from fiscal 2027 onward, when volume yield, customer count and timing all come together.
Article Summary
- What decides a foundry's fate is customers, not the fab. Rapidus is in talks with more than 60 companies and now provides PDKs to about 10 (media-reported).
- A PDK (process design kit) is the specification set needed to design on a fab's process — handing it over is the practical entry point of customer acquisition.
- Chip design needs an ecosystem of EDA (design tools) and IP (reusable components), which TSMC spent decades building.
- Rapidus is betting on high-mix low-volume, short-TAT production rather than mass production, targeting diverse AI and edge demand.
- Whether the strategy pays off will be tested from fiscal 2027 onward, when volume yield, customer count and timing all come together.
Frequently Asked Questions (FAQ)
Q.What is a PDK (process design kit)?+
A PDK (Process Design Kit) is the complete set of specifications, components and rules needed to design a semiconductor for a specific fab's manufacturing process. It includes transistor characteristics data, wiring rules, and component libraries for verification — designers need it before they can draw any circuit for that fab. Handing over a PDK means opening the door and saying 'design on our 2nm process,' making it the practical entry point of customer acquisition.
Q.How many customers is Rapidus talking to?+
According to Rapidus president Atsuyoshi Koike, the company is in talks with more than 60 prospective customers, mainly in HPC (high-performance computing), AI and edge applications, and has moved to providing PDKs to about 10 of them (media-reported). These are not signed contracts or confirmed production wins — they are companies that have advanced to the stage of trial design. Foundry businesses grow volume orders out of exactly this kind of pipeline.
Q.Why are customers harder than fabs for a foundry?+
Because even the most advanced fab cannot recoup its investment without customers designing and manufacturing there — utilization stays low and the capital sits idle. Chip design requires an ecosystem of design tools (EDA) and reusable components (IP), which TSMC spent decades building. A new foundry has to earn customer trust in its design environment from scratch, and that is the hardest barrier.
Q.How does the Rapidus strategy differ from TSMC's?+
Rather than TSMC-style mass production that drives prices down with scale, Rapidus is betting on high-mix low-volume production with short turnaround times (short TAT). By drastically shortening the period from design to prototype and running many product types in small lots, it aims to serve diverse AI and edge demand. Whether the strategy is commercially viable will be tested from fiscal 2027 onward, when volume yield and customer count come together.
Glossary
References & Sources
- ラピダス小池社長が語る顧客獲得の現在地——60社以上と協議、約10社にPDK提供News mediaITmedia MONOist (2026-03-02) — Cited for: CEO発言:HPC・AI・エッジ中心に60社以上と協議、うち約10社にPDK等を提供(Nikkei xTech・METI進捗資料で裏付け・報道ベース)。少量多品種・短TAT戦略https://monoist.itmedia.co.jp/mn/articles/2603/02/news062.html
- ラピダスに対する追加助成の決定について(2nm世代の量産に向けた前工程・後工程の技術開発)GovernmentIPA(情報処理推進機構) (2026-06-05) — Cited for: 2026-06-05にIPA経由で政府から1500億円の追加出資(IPA累計2500億円)・2027年度半ばの2nm量産に向けた前工程/後工程の技術開発支援(一次)https://www.ipa.go.jp/pressrelease/2026/press20260605-3.html
- NEDO Approves Rapidus' FY2026 Plan and Budget for 2nm Semiconductor ProjectsPrimary sourceRapidus Corporation(公式リリース) (2026-04-11) — Cited for: IIM-1(千歳・北海道)の場所・2025年の試作ライン稼働・300mmでの2nm GAA動作確認・FY2026計画承認(2026-04-11)(要確認)https://www.rapidus.inc/en/news_topics/information/nedo-approves-rapidus-fy2026-plan-and-budget-for-2nm-semiconductor-projects/
- Rapidus株式会社の実施計画の概要(特定半導体生産施設整備等計画)Government経済産業省(METI) (2025) — Cited for: 2027年度後半に2nm量産開始・2031年度頃の上場目標という政府承認の実施計画(要確認)https://www.meti.go.jp/policy/mono_info_service/joho/laws/josokuho/josokuho_jisshikeikaku.pdf
- Rapidus to start construction on 1.4nm fab in 2027 — R&D on node to begin next yearNews mediaTom's Hardware (2025-11) — Cited for: Rapidusの1.4nmプロセス開発2026年開始・第2工場2027年着工・2029年頃量産の計画。小池社長がAI/ロボティクス/エッジ向けに60社超の見込み顧客と協議中https://www.tomshardware.com/tech-industry/rapidus-to-start-construction-on-1-4nm-fab-in-2027-research-and-development-on-node-to-begin-next-year
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